Why Hybrid Integration and 200G/lane Are the Paths Forward for Optical Data Communications Industry

April 22nd, 2024

Of the many things artificial intelligence has upended, the microchips industry may be the sector that has seen the most disruption. AI is gluttonous for speed and power and as the computing industry has raced to meet the demand, it has become clear that existing solutions will not be adequate. There is a growing sense of urgency across the industry as it becomes increasingly clear that optical interconnects enable large-scale AI compute and other data-intensive workloads to operate at bandwidths, energy efficiencies, and latencies that are today unachievable through electrical-based interconnect technology.

Sixty-plus years after engineers commercialized the first monolithic integrated circuit chip, the explosion of AI and the insatiable demand that data center hyperscalers have for more bandwidth has presented a remarkable opportunity for chipmakers to move beyond traditional solutions in a dramatic way. While materials such as indium phosphide and gallium arsenide have been used in commercial applications for decades, the growth of material-agnostic optical platforms has presented the chance to transition from “silicon-only” to “silicon-plus” designs. Whereas the absolute need for silicon will never wane, the slowing of Moore’s law has opened the door to “augmented silicon” technologies where the innate capabilities and advantages of silicon are augmented through incorporation of new materials (such as germanium and indium phosphide), new architectures (like chiplet and hybrid system partitioning) and 3D packaging and assembly. That’s the reality many manufacturers and industry observers have realized so far in the 2020s.

One of the ascendent technologies is photonics. Many companies are in the midst of identifying optical computing solutions that will drive the next generation of device manufacturing.

Here are three key areas where photonics — which was once a boutique niche — is positioned to be the catalyst for large-scale growth in hardware applications for AI and hyperscale data centers.

1. Hybrid Integration:
With a hybrid-integration approach to wafer-scale chip design, developers can assure those manufacturers who have built their entire operations around silicon that the coming wave of product design will have a number of familiar pieces. Hybrid integration allows for a seamless transition to the ways of the future. 

At POET Technologies, our “semiconductorization of photonics” approach is a form of hybrid integration. That term is meant to underscore the point of our designs, which is to make it as straightforward as possible for the semiconductor industry to move to photonics-first solutions that are material agnostic. Our elegant design eliminates dozens of parts because we rely on passively attached optical components to move data leveraging the broad semiconductor industry’s investments in advanced packaging technology. Based on a “silicon for photonics” interposer platform, POET’s products offer manufacturers a critical piece to achieving high integration, especially for 1.6T, 3.2T, and beyond. With its “silicon for photonics” hybrid integration approach POET is focused on addressing the shortcomings of more conventional SiPhotonics solutions  with features like passive alignments, low-loss multi-layer waveguides, and integrated optical passives like multiplexers and de-multiplexers that have the flexibility and fungibility to address a broad range of market requirements.

Such flexibility and integration is crucial because serial data communication channels have not been able to keep up with the pace of bandwidth growth. The number of communications lanes increase as data rate increases and those manufacturers who rely on conventional discrete assembly are challenged to economically deploy products that perform consistently within eight-channel architecture, which is needed for 800G speeds, and are incapable of accommodating 16-channel lanes, which is necessary for 1.6T and 3.2T, the speeds of the future. 

The way in which POET achieves 16-lane capability is through the use of 3D assembly techniques and stacked non-interacting waveguides. It’s a simplified process that drives data communications at unprecedented rates of speed.

2. 200G/Lane:
Moving data simultaneously through 16 lanes is one way that photonics brings superior capability to the market and another is its ability to double the speed that can go through each of those lanes. Conventional speeds are currently 100G/lane but photonics can operate at 200G/lane, which busts the bottlenecks that cause latency and high power consumption. At 200G/lane, AI and hyperscale data center and cloud networks can surge toward new capacity limits.

Among the giants touting the merits of 200G/lane solutions is Broadcom, which demoed an optical transmission link using that configuration at OFC 2023. 

“The demo not only validated the feasibility of 200G/lane optical links for data center networking, but also reassured the ecosystem that 1.6T optical modules can cost effectively be deployed to address the growing bandwidth demands in data centers supporting AI applications and workloads,” wrote Broadcom master engineer Khanh Lam

A key component needed to achieve 200G/lane is an externally modulated laser (EML). Already, more than 90% of 800G modules in production today use EMLs, which present the primary path to 200G/lane solutions. The performance of EMLs and the industry trust they have attained are reasons why POET has retooled its optical interposer platform to include both EML and DML (directly modulated laser) solutions.

3. Disaggregation: “Chip disaggregation, or chiplets, offers an alternative to the traditional monolithic SoC scaling approach. Aggregating multiple chiplets to perform the function of a single monolithic IC de-risks the overall system by reducing complexity and increasing yields,” writes chip-producer Rambus.

With the conventional processor-centric computing architecture and copper interconnects, the chips based on 3nm technology that have dominated semiconductor design for decades are approaching their physical limitations. The necessity for faster data transmission has gone beyond what these chips can capably deliver. As a result, disaggregation is going to push the need for photonic connectivity. It is already happening at Google, whose AI servers are exploiting disaggregation to connect to networks with 800G transceivers — making the search-engine leader the first company to commit to using that speed for its data centers.

Products such as the POET Infinity™ chiplet, and the family of engines built from them, provide an answer for pluggable transceiver and module designs. A 400G transmitter chiplet, the Infinity can be configured in a daisy-chain architecture to reach speeds of 800G (2x400G chiplets), 1.6T (4x400G), and beyond. As with all products built from the POET Optical Interposer, the Infinity chiplet includes a monolithically integrated multiplexer, and eliminates wire bonds and active alignments of components.

Photonics-first innovations such as those being introduced to the market by POET and other companies promise to pave a new path forward in the AI era. The industry is in the middle of an important stage as it develops new processes to power computing performance. The platforms and products that gain adoption now are likely to be the de facto choices for chipmakers for decades to come.

[This article was first published in PIC Magazine in March 2024]

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